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Syllabus

NEC Electronics · Practice

Chapters & sets

1. Basic Electrical and Electronics Engineering

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded Systems

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Computer Networks and Network Security

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

10. Project Planning, Design and Implementation

Mixed chapter MCQs Set 1

50 questions

Question 1

A time-sharing system implies:

A.
More than one processor in the memory
B.
More than one program in the memory
C.
More than one memory in the system
D.
None of above

Question 2

A multiprocessor computer is of the type:

A.
SISD
B.
MIMD
C.
SIMD
D.
All of the above

Question 3

Microprocessor is a device which has at least:

A.
Memory
B.
Registers
C.
I/O devices
D.
CPU

Question 4

A supercomputer has the capabilities of execution:

A.
Pipeline instruction
B.
Floating point arithmetic operation
C.
Vector instruction
D.
All of the above

Question 5

The maximum stages in pipelining architecture are:

A.
4
B.
6
C.
2
D.
5

Question 6

Instruction pipelining has minimum stages:

A.
4
B.
6
C.
2
D.
3

Question 7

Systems do not have parallel processing capabilities are:

A.
SISD
B.
MIMD
C.
SIMD
D.
All of the above

Question 8

Memory access in RISC architecture is limited to instructions:

A.
CALL & RET
B.
STA & LDA
C.
PUSH & POP
D.
MOV & JMP

Question 9

Interrupt which are initiated by an I/O device are:

A.
Internal
B.
Software
C.
External
D.
All of the above

Question 10

Interrupt which are initiated by an instruction are:

A.
Hardware
B.
Internal
C.
External
D.
Software

Question 11

States bit of the CPU are stored in a flag:

A.
Carry
B.
Zero
C.
Sign
D.
All of the above

Question 12

The effective address is the address of the operand in an instruction of type:

A.
Immediate
B.
Register
C.
Indirect
D.
Computational

Question 13

Program counter of a CPU stores the address of the instruction:

A.
Currently executed
B.
Just executed
C.
To be executed next
D.
None of the above

Question 14

A stack-organized computer has:

A.
Three-address instruction
B.
One-address instruction
C.
Two-address instruction
D.
Zero-address instruction

Question 15

The operation performed on stack are:

A.
IN & OUT
B.
PUSH & POP
C.
CALL & RET
D.
POP & OUT

Question 16

The stack is the list of type:

A.
LIFO
B.
FILO
C.
LILO
D.
All of the above

Question 17

A microprocessor consists of:

A.
Control unit
B.
ALU
C.
Program counter
D.
All of the above

Question 18

A microprocessor sequencer performs the operation:

A.
Read
B.
Execute
C.
Write
D.
Read and execute

Question 19

A microprogram written as a string of 0's and 1's is a:

A.
Symbolic microinstruction
B.
Binary microprogram
C.
Binary microinstruction
D.
All of the above

Question 20

The branch logic that provides decision-making capabilities in the control unit is known as:

A.
Controlled transfer
B.
Unconditional transfer
C.
Conditional transfer
D.
None of the above

Question 21

A control unit whose binary control variables are stored in memory is known as:

A.
Hardwired control unit
B.
Software control unit
C.
Micro-programmed control unit
D.
Hardware control unit

Question 22

During execution, subroutine return address is stored in:

A.
Control address register
B.
Stack pointer
C.
Subroutine address
D.
Memory location

Question 23

The next address generator is sometimes called a:

A.
Instruction sequence
B.
Micro program sequence
C.
Program sequence
D.
Translator

Question 24

The control data register holds the present microinstruction and is sometimes called:

A.
Instruction register
B.
Sequence register
C.
Microinstruction register
D.
Pipeline register

Question 25

A memory that is a part of a control unit is referred to as:

A.
External memory
B.
Cache memory
C.
Internal memory
D.
Control memory

Question 26

Whenever POP H instruction is executed:

A.
Data byte in the HL pair are stored on the stack
B.
Two data bytes at the top of the stack are transferred to the HP register pair
C.
Two data bytes at the top of the stack are transferred to the program counter
D.
Two data bytes from the HL register that were previously stored on the stack are transferred back to the HL pointer

Question 27

When the RET instruction at the end of a subroutine is executed:

A.
The information where the stack is initialized is transferred to the stack pointer
B.
The memory address of the RET instructions is transferred to the program counter
C.
Two data bytes stored in the top two locations of the stack are transferred to the program counter
D.
Two data bytes stored in the top two locations of the stack are transferred to the stack pointer

Question 28

When a subroutine is called, the address of the instruction following the CALL is stored in/on the:

A.
Stack pointer
B.
Program counter
C.
Accumulator
D.
Stack

Question 29

A stack pointer is:

A.
A 16-bit register in the microprocessor that indicates the beginning of the stack memory
B.
A register that decodes and executes 16-bit arithmetic expressions
C.
The first memory locations where a subroutine address is stored
D.
A register in which flag bits are stored

Question 30

A stack is:

A.
An 8-bit register in the microprocessor
B.
A set of memory locations in R/WM reserved for storing information temporarily during the execution of a program
C.
A 16-bit memory address stored in the program counter
D.
A 16-bit register in the microprocessor

Question 31

A third and last component of CPU is:

A.
ALU
B.
Supervisor – control unit
C.
Input device
D.
Register unit

Question 32

The section of the CPU that selects, interprets, and sees to the execution of program instructions is:

A.
Memory
B.
Control unit
C.
Register unit
D.
ALU

Question 33

A device used to bring information into a computer is:

A.
ALU
B.
Control unit
C.
Input device
D.
Output device

Question 34

A microprocessor is a..... on a chip:

A.
Computer
B.
ALU
C.
CPU
D.
Control unit

Question 35

Part of the computer where the data and instructions are held is:

A.
Register unit
B.
Memory unit
C.
Accumulator
D.
CPU

Question 36

Backing storage is so named because:

A.
It is always kept at the back of the CPU
B.
It backs up the computer's main memory
C.
It lags behind the main memory
D.
It is slow and backward

Question 37

The ALU and control unit of most of the microcomputers are combined and manufactured on a single silicon chip. What is it called?

A.
Monochip
B.
ALU
C.
Microprocessor
D.
Control unit

Question 38

Which of the following code used in present-day computing was developed by IBM corporation?

A.
ASCII
B.
Baudot code
C.
Hollerith code
D.
EBCDIC CODE

Question 39

Which parts of the computer are used for calculating and comparing?

A.
Disk unit
B.
ALU
C.
Control unit
D.
Modem

Question 40

Instruction LXI in 8085 loads:

A.
Stack pointer
B.
None of the above
C.
Register pair
D.
All of the above

Question 41

A CALL instruction is always encountered by instructions:

A.
IN
B.
OUT
C.
RET
D.
INTR

Question 42

In I/O mapped I/O 8085 duplicates the I/O address on:

A.
Address and data line
B.
Lower byte of address and control line
C.
Lower and higher byte of address
D.
Higher byte of address and data line

Question 43

Address and data line in 8085 are:

A.
Separate lines
B.
Only lower byte of address is multiplexed
C.
Common line
D.
Shared line

Question 44

The 16-bit register in 8085 is:

A.
General purpose register
B.
Stack pointer and program counter
C.
Accumulator
D.
All of the above

Question 45

Microprocessor 8085 can address location up to:

A.
32K
B.
64K
C.
128K
D.
1M

Question 46

Pipeline processing implements:

A.
Fetch instructions
B.
Fetch operand
C.
Decode instruction
D.
All of the above

Question 47

Pipeline strategy is called implement:

A.
Instruction execution
B.
Instruction decoding
C.
Instruction pre-fetch
D.
Instruction manipulation

Question 48

Intel 80486 pipelining implements stages:

A.
6
B.
5
C.
4
D.
3

Question 49

Pipeline processing uses the technique:

A.
Sharing the memory
B.
Pre-fetching
C.
Bit slicing
D.
Parallel processing

Question 50

Micro instructions are stored in:

A.
Computer memory
B.
Secondary storage
C.
Primary memory
D.
Control memory

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