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Syllabus

NEC Electronics · Practice

Chapters & sets

1. Basic Electrical and Electronics Engineering

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded Systems

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Computer Networks and Network Security

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

10. Project Planning, Design and Implementation

Digital Logic Set 11

50 questions

Question 1

The output of an OR gate is HIGH when

A.
Any input is HIGH
B.
No inputs are HIGH
C.
All inputs are HIGH
D.
Both answers (A) and (C)

Question 2

How many 3 lines to 8 line decoder are required for a 1 of 32 decoder?

A.
1
B.
4
C.
8
D.
16

Question 3

Convert BCD 0001 0010 0110 to binary

A.
1111110
B.
1111101
C.
1111000
D.
1111111

Question 4

How many data select lines are required for selecting eight inputs?

A.
1
B.
2
C.
3
D.
4

Question 5

How many 1 -of-16 decoders are required for decoding a 7 bit binary number?

A.
5
B.
6
C.
7
D.
8

Question 6

The implementation of simplified sum- of – products expressions may be easily implemented into actual logic circuits using all universal ……gates with little or no increase in circuit complexity.

A.
AND/OR
B.
NAND
C.
NOR
D.
OR/AND

Question 7

Which of the following combinations cannot be combined into k-map groups?

A.
Corners in the same row
B.
Corners in the same column
C.
Diagonal corners
D.
Overlapping combinations

Question 8

Which gate is best used as a basic comparator?

A.
NOR
B.
OR
C.
XOR
D.
AND

Question 9

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

A.
A > B = 1, A < B = 0, A < B = 1
B.
A > B = 0, A < B = 1, A = B = 0
C.
A > B = 1, A < B = 0, A = B = 0
D.
A > B = 1, A < B = 0, A = B = 0

Question 10

A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

A.
The output of the gate appears to be open
B.
The dim indication on the logic probe indicates that the supply voltage is probably low
C.
The dim indication is a result of a bad ground connection on the logic probe
D.
The gate may be a tri state logic.

Question 11

Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output?

A.
$(\sum_2 \sum_3 \sum_2 \sum_1 = 0111), (C_{out} = 0)$
B.
$(\sum_2 \sum_3 \sum_2 \sum_1 = 1111), (C_{out} = 1)$
C.
$(\sum_2 \sum_3 \sum_2 \sum_1 = 1011), (C_{out} = 1)$
D.
$(\sum_2 \sum_3 \sum_2 \sum_1 = 1100), (C_{out} = 1)$

Question 12

Each "1" entry in a K-map square represents:

A.
A HIGH for each input truth table condition that produces a HIGH output.
B.
A HIGH output on the truth table for all LOW input combinations.
C.
A LOW output for all possible HIGH input conditions.
D.
A DON'T CARE condition for all possible input truth table combinations.

Question 13

Looping on a k-map always results in the elimination of:

A.
Variables within the loop that appear only in their complemented form
B.
Variables that remain unchanged within the loop
C.
Variables within the loop that appear in both complemented and uncomplemented form
D.
Variables within a loop that appear only in their un complemented form

Question 14

The carry output of a half-adder circuit can be expressed as......

A.
$(C_{out} = AB)$
B.
$(C_{out} = A + B)$
C.
$(C_{out} = A \oplus B)$
D.
None of the above

Question 15

What is the major difference between half-adders and full-adders?

A.
Nothing basically; full-adders are made up of two half-adders.
B.
Full adders can handle double-digit numbers.
C.
Full adders have a carry input capability.
D.
Half adders can handle only single-digit numbers.

Question 16

Manipulation of individual bits of a word is often referred to as

A.
Bit twidding
B.
Bit swapping
C.
Micro operation
D.
None of the above

Question 17

The ASCII code for letter A is

A.
1100011
B.
100000
C.
1111111
D.
0010011

Question 18

Which gate can be used as anti-coincidence detector?

A.
X -NOR
B.
NAND
C.
X -OR
D.
NOR

Question 19

Which of the following is a self-complementing code?

A.
8421 code
B.
5211 code
C.
Gray code
D.
Binary code

Question 20

Excess 3 code is also known as:

A.
Weighted code
B.
Self-complementing code
C.
Cyclic redundancy code
D.
Algebraic code

Question 21

Binary equivalent of gray code number 101 is

A.
101
B.
110
C.
100
D.
111

Question 22

Which of the following expression is in the product-of-sums form?

A.
(A + B) (C + D)
B.
(AB) (CD)
C.
AB (CD)
D.
B + CD

Question 23

Which of the following expressions is in the sum-of-products form?

A.
(A + B) (C + D)
B.
(AB) (CD)
C.
AB (CD)
D.
AB + CD

Question 24

Which statement below best describes a Karnaugh map?

A.
A Karnaugh map can be used to replace Boolean rules.
B.
The Karnaugh map eliminates the need for using NAND and NOR gates.
C.
Variable complements can be eliminated by using Karnaugh maps.
D.
Karnaugh maps provide a visual approach to simplifying Boolean expressions.

Question 25

A decoder can be used as a de-multiplexer by

A.
tying all enable pins LOW
B.
tying all data-select lines LOW
C.
tying all data-select lines HIGH
D.
using the input lines for data selection and an enable line for data input

Question 26

How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 300:0?

A.
1
B.
2
C.
3
D.
4

Question 27

A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?

A.
0
B.
3
C.
9
D.
None of the above

Question 28

A full-adder has a Cin = 0. What are the sum

((\Sigma))

and the carry (Cout) when A = 1 and B = 1?

A.
$(\Sigma = 0), (C_{out} = 0)$
B.
$(\Sigma = 0), (C_{out} = 1)$
C.
$(\Sigma = 1), (C_{out} = 0)$
D.
$(\Sigma = 1), (C_{out} = 1)$

Question 29

Which of the following gates is a series circuit gate?

A.
AND GATE
B.
OR GATE
C.
XOR GATE
D.
None of the above

Question 30

A+B can be implemented by

A.
NAND gate alone
B.
Both (A) and (B)
C.
NOR gate alone
D.
None of the above

Question 31

Which of the following logic expression is incorrect?

A.
$1(\oplus)0 = 1$
B.
$(\oplus)1 (\oplus)0 = 1$
C.
$1 (\oplus)1 (\oplus)1 = 1$
D.
$1 (\oplus)1 = 0$

Question 32

Let x and y be the input and z be the output of NAND gate. The value of Z is given by:

A.
x.y
B.
x+y
C.
x+y
D.
None of the above

Question 33

(NOR) (XOR) (NAND) =

A.
NOR
B.
XOR
C.
NAND
D.
XNOR

Question 34

The total number of Boolean functions which can be realized with four variables is

A.
4
B.
256
C.
17
D.
65,536

Question 35

The Boolean function A + BC is reduced form of...

A.
AB + BC
B.
A B + ABC
C.
(A+B) (A+C)
D.
(A+C) B

Question 36

The logical expression y = A + A B is equivalent to...

A.
Y = AB
B.
Y = A' + B
C.
Y = A+B
D.
Y = A B

Question 37

What is the maximum number of different Boolean functions involving n Boolean variables?

A.
$( n^2 )$
B.
$( 2^{2^n} )$
C.
$( 2^n )$
D.
$( 2^{2^n} )$

Question 38

With three variables maximum possible logical expression is:

A.
6
B.
512
C.
256
D.
65536

Question 39

In n variables maximum possible dual expression is:

A.
$( n^2 )$
B.
$( 2^{2^n-1} )$
C.
$( 2^n )$
D.
$(2^{n^2})$

Question 40

Which of the following expression is not equivalent to x

A.
X NAND x
B.
X NAND 1
C.
X NOR X
D.
X NOR 1

Question 41

The address bus width of a memory of size 1024 x 8 bits is

A.
8 bits
B.
13 bits
C.
10 bits
D.
15 bits

Question 42

The final step in designing the combinational circuit is

A.
To determine the input and output variables
B.
To draw the truth table
C.
To minimize the Boolean function for each output obtained
D.
To draw the minimized logic diagram

Question 43

The fetching, decoding and executing of an instruction is broken down into several time intervals. Each of these intervals, involving one or more clock period is called

A.
Instruction cycle
B.
Machine cycle
C.
Process cycle
D.
None of the above

Question 44

A combinational circuit consist of

A.
Logic gate and memory elements
B.
Logic gates only
C.
Memory elements only
D.
None of the above

Question 45

Full adder circuit can be implemented by

A.
Multiplexer
B.
AND and OR gates
C.
Half adders
D.
Decoders

Question 46

How many full adders are required to construct an m-bit parallel adders?

A.
m
B.
m/2
C.
m-1
D.
m+1

Question 47

select the statement that best describes the parity method of error detection:

A.
Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
B.
Arity checking is not suitable for detecting single-bit errors in transmitted codes.
C.
Parity checking is best suited for detecting single-bit errors in transmitted codes
D.
Parity checking is not suitable for detecting single-bit errors in transmitted codes.

Question 48

A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n)

A.
EX-NOR gate
B.
OR gate
C.
EX-OR gate
D.
NAND gate

Question 49

A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):

A.
EX-NOR gate
B.
OR gate
C.
EX-OR gate
D.
NAND gate

Question 50

Identify the type of gate below from the equation

( X = A \oplus B = \overline{A}B + AB )

A.
OR GATE
B.
NOR GAT
C.
EX-OR GAT
D.
NAND GATE

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