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Syllabus

NEC Electronics · Practice

Chapters & sets

1. Basic Electrical and Electronics Engineering

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded Systems

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Computer Networks and Network Security

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

10. Project Planning, Design and Implementation

Microprocessor Set 5

50 questions

Question 1

The most common addressing techniques employed by a CPU is:

A.
Direct
B.
Indirect
C.
Immediate
D.
All of these

Question 2

______ have been developed specifically for pipelined systems.

A.
Utility software
B.
Speed up utilities
C.
Optimizing compilers
D.
None of the mentioned

Question 3

The pipelining process is also called as______.

A.
Superscalar operation
B.
Assembly line operation
C.
Von Neumann cycle
D.
None of the mentioned

Question 4

Each stage in pipelining should be completed within ______ cycle.

A.
1
B.
2
C.
3
D.
4

Question 5

To increase the speed of memory access in pipelining, we make use of______.

A.
Special memory locations
B.
Special purpose registers
C.
Cache
D.
Buffers

Question 6

The contention for the usage of a hardware device is called______.

A.
Structural hazard
B.
Stalk
C.
Deadlock
D.
None of the mentioned

Question 7

The situation wherein the data of operands are not available is called______.

A.
Data hazard
B.
Stock
C.
Deadlock
D.
Structural hazard

Question 8

The CISC stands for______.

A.
Computer Instruction Set Complement
B.
Complete Instruction Set Complement
C.
Computer Indexed Set Components
D.
Complex Instruction Set Computer

Question 9

The computer architecture aimed at reducing the time of execution of instructions is______.

A.
CISC
B.
RISC
C.
ISA
D.
ANNA

Question 10

The iconic feature of the RISC machine among the following is______.

A.
Reduced number of addressing modes
B.
Increased memory size
C.
Having a branch delay slot
D.
All of the mentioned

Question 11

Both the CISC and RISC architectures have been developed to reduce the______.

A.
Cost
B.
Time delay
C.
Semantic gap
D.
All of the mentioned

Question 12

Pipe-lining is a unique feature of ______.

A.
RISC
B.
CISC
C.
ISA
D.
IANA

Question 13

In CISC architecture most of the complex instructions are stored in ______.

A.
Register
B.
Diodes
C.
CMOS
D.
Transistors

Question 14

In ______ the operand is specified in the instruction itself.

A.
Immediate addressing
B.
Register mode
C.
Implied addressing
D.
Register Indirect

Question 15

In which mode the operand is placed in one of 8-bit or 16-bit general-purpose registers?

A.
Immediate addressing
B.
Register mode
C.
Implied addressing
D.
Register Indirect

Question 16

An offset is determined by adding any combination of ______ address elements.

A.
3
B.
4
C.
5
D.
6

Question 17

Zero address instruction are designed with implied addressing mode.

A.
TRUE
B.
FALSE
C.
Can be true or false
D.
Cannot say

Question 18

In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is ______.

A.
EA = 5 + R1
B.
EA = R1
C.
EA = \[R1]
D.
EA = 5 + \[R1]

Question 19

The addressing mode/s, which uses the PC instead of a general-purpose register is ______.

A.
Indexed with offset
B.
Relative
C.
Direct
D.
Both indexed with offset and direct

Question 20

______ addressing mode is most suitable to change the normal sequence of execution of instructions.

A.
Relative
B.
Indirect
C.
Index with Offset
D.
Immediate

Question 21

Sign magnitude is a very simple representation of?

A.
Positive number
B.
Negative numbers
C.
Infinity
D.
Zero

Question 22

Sign bit 1 represents

A.
Positive number
B.
FALSE
C.
TRUE
D.
Negative Number

Question 23

The logic 1 in positive logic system is represented by?

A.
Zero voltage
B.
Lower voltage level
C.
Higher voltage level
D.
Negative voltage

Question 24

The m-bit parallel adder consists of

A.
m full adders
B.
m+1 full adders
C.
m-1 full adders
D.
m/2 full adders

Question 25

Input or output devices that are connected to a computer are called ______.

A.
Input/Output Subsystem
B.
Peripheral Devices
C.
Interfaces
D.
Interrupt

Question 26

How many types of modes of I/O Data Transfer?

A.
2
B.
3
C.
4
D.
5

Question 27

The method which offers higher speeds of I/O transfers is ______.

A.
Interrupts
B.
Memory mapping
C.
Program-controlled I/O
D.
DMA

Question 28

In memory-mapped I/O ______.

A.
The I/O devices have a separate address space
B.
The I/O devices and the memory share the same address space
C.
A part of the memory is specifically set aside for the I/O operation
D.
The memory and I/O devices have an associated address space

Question 29

The ISA is an architectural standard developed by ______.

A.
IBM
B.
AT\&T Labs
C.
Microsoft
D.
Oracle

Question 30

The SCSI BUS is used to connect the video devices to a processor by providing a ______.

A.
Single Bus
B.
USB
C.
SCSI
D.
Parallel BUS

Question 31

The registers of the controller are ______.

A.
16 bit
B.
32 bit
C.
64 bit
D.
128 bit

Question 32

Auxiliary memory access time is generally ______ times that of the main memory.

A.
10
B.
100
C.
1000
D.
10000

Question 33

What is the formula for Hit Ratio?

A.
Hit/(Hit + Miss)
B.
Miss/(Hit + Miss)
C.
(Hit + Miss)/Miss
D.
(Hit + Miss)/Hit

Question 34

Which of the following is correct example for Auxiliary Memory?

A.
Magnetic disks
B.
Tapes
C.
Flash memory
D.
Both A and B

Question 35

The fastest data access is provided using ______.

A.
Cache
B.
DRAM's
C.
SRAM's
D.
Registers

Question 36

The next level of memory hierarchy after the L2 cache is ______.

A.
Secondary storage
B.
Main memory
C.
Register
D.
TLB

Question 37

Which Processors includes multicolcks?

A.
Complex Instruction Set Computer
B.
Reduced Instruction Set Computer
C.
ISA
D.
ANNA

Question 38

Which Processors Data transfer Register to register?

A.
Complex Instruction Set Computer
B.
Reduced Instruction Set Computer
C.
ISA
D.
ANNA

Question 39

Which of the following is true?

A.
The RISC processor has a more complicated design than CISC.
B.
RISC Focus on software
C.
CISC Focus on software
D.
RISC has Variable sized instructions

Question 40

Which processor requires more number of registers?

A.
CISC
B.
ISA
C.
RISC
D.
ANNA

Question 41

Both the CISC and RISC architectures have been developed to reduce the ______.

A.
Semantic gap
B.
Time Delay
C.
Cost
D.
Reduced Code

Question 42

Which of the following is true about CISC processor?

A.
Micro programmed control unit is found in CISC.
B.
Data transfer is from memory to memory.
C.
In this instructions are not register based.
D.
All of the above

Question 43

What is the high-speed memory between the main memory and the CPU called?

A.
Register Memory
B.
Cache Memory
C.
Storage Memory
D.
Virtual Memory

Question 44

Cache Memory is implemented using the DRAM chips.

A.
True
B.
False

Question 45

Whenever the data is found in the cache memory it is called as ______.

A.
HIT
B.
MISS
C.
FOUND
D.
ERROR

Question 46

LRU stands for ______.

A.
Low Rate Usage
B.
Least Rate Usage
C.
Least Recently Used
D.
Low Required Usage

Question 47

When the data at a location in cache is different from the data located in the main memory, the cache is called ______.

A.
Unique
B.
Inconsistent
C.
Variable
D.
Fault

Question 48

Which of the following is not a write policy to avoid Cache Coherence?

A.
Write through
B.
Write within
C.
Write back
D.
Buffered write

Question 49

Which of the following is an efficient method of cache updating?

A.
Snoopy writes
B.
Write through
C.
Write within
D.
Buffered write

Question 50

In ______ mapping, the data can be mapped anywhere in the Cache Memory.

A.
Associative
B.
Direct
C.
Set Associative
D.
Indirect

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