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Syllabus

NEC Electronics · Practice

Chapters & sets

1. Basic Electrical and Electronics Engineering

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded Systems

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Computer Networks and Network Security

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

10. Project Planning, Design and Implementation

Digital Logic Set 12

32 questions

Question 1

Parity systems are defined as either ______ or ______ and will add an extra ______ to the digital information being transmitted.

A.
Positive, negative, byte
B.
Odd, even, bit
C.
Upper, lower, digit
D.
On, off, decimal

Question 2

Which type of gate can be used to add two bits?

A.
EX-OR
B.
EX-NOR
C.
EX-NAND
D.
None of the above

Question 3

Why is an exclusive-NOR gate also called an equality gate?

A.
The output is false if the inputs are equal.
B.
The output is true if the inputs are opposite.
C.
The output is true if the inputs are equal.
D.
None of the above

Question 4

Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function.

A.
Using A as the control, when ( A = 0, X ) is the same as B. When ( A = 1, X ) is the same as B.
B.
Using a as the control, when ( a = 0, X ) is the same as B. When ( A = 1, X ) is the inverse of B
C.
Using A as the control, when ( A = 0, X ) is the inverse of B. When ( A = 1, X ) is the same as B
D.
Using A as the control, when ( A = 0, X ) is the inverse of B. When ( A = 1, X ) is the inverse of B

Question 5

Determine odd parity for each of the following data words: 1011101 11110111 1001101

A.
P = 1, P = 1, P = 0
B.
P = 0, P = 0, P = 0,
C.
P = 1, P = 1, P = 1
D.
P = 0, P = 0, P = 1

Question 6

The Ex-NOR is sometimes called the ______.

A.
Parity gate
B.
Equality gate
C.
Inverted gate
D.
Parity gate or the equality gate

Question 7

Determine the values of A, B, C, and D that make the sum term

( \overline{A} + \overline{B} + \overline{C} + D )

equal to zero.

A.
A = 1, B = 0, C = 0, D = 0
B.
A = 1, B = 0, C = 1, D = 0
C.
A = 0, B = 1, C = 0, D = 0
D.
A = 1, B = 0, C = 1, D = 1

Question 8

An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)______ gate.

A.
NOT
B.
OR
C.
NOR
D.
NAND

Question 9

For the SOP expression , how many 1s are in the truth table's output column

A.
1
B.
2
C.
3
D.
4

Question 10

A truth table for the SOP expression has how many input combinations?

A.
1
B.
2
C.
4
D.
8

Question 11

How many gates would be required to implement the following Boolean expression before simplification? XY + X(X + Z) + Y(X + Z)

A.
1
B.
2
C.
3
D.
5

Question 12

In canonical SOP form, the number of min terms in logical expression , A + B'C is:

A.
4
B.
5
C.
6
D.
7

Question 13

How many gates would be required to implement the following Boolean expression after simplification? XY + X(X + Z) + Y(X + Z)

A.
1
B.
2
C.
3
D.
5

Question 14

Which Boolean algebra property allows us to group operands in an expression in any order without affecting the results of the operation \[for example, A + B = B + A]?

A.
Associative
B.
Commutative
C.
Boolean
D.
Distributive

Question 15

Applying DeMorgan's theorem to the expression

( (X + Y) + \overline{Z} )

, we get ______

A.
( (X + Y)Z )
B.
( (X' + Y')Z )
C.
( (X + Y)Z' )
D.
( (X' + Y')Z' )

Question 16

Use Boolean algebra to find the most simplified SOP expression for F = ABD + CD + ACD + ABC + A BCD.

A.
F = ABD + ABC + CD
B.
F = CD + AD
C.
F = BC + AB
D.
F = AC + AD

Question 17

In a sequential circuit the next state is determined ………and……

A.
State variable, current state
B.
Current state, flip-flop output
C.
Current state and external input
D.
Input and clock signal applied

Question 18

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

A.
Mod -6, Mod-10
B.
Mod -50, Mod -10
C.
Mod 10, Mod-50
D.
Mod-50, Mod -6

Question 19

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ___ of the flip-flop.

A.
Set -up time
B.
Hold time
C.
Pulse interval time
D.
Pulse stability time (PST)

Question 20

___ is said to occur when multiple internal variables change due to change in one input variable.

A.
Race condition
B.
Hold delay
C.
Hold and wait
D.
Clock skew

Question 21

A decade counter is.....

A.
Mode-3 counter
B.
Mod-5 counter
C.
Mod-8 counter
D.
Mod-10 counter

Question 22

A nibble consist of.....bits

A.
2
B.
4
C.
8
D.
16

Question 23

Excess-8 code assigns to "-8 "

A.
1110
B.
1100
C.
1000
D.
0000

Question 24

The three fundamentals gates are:

A.
AND, NAND, NAND
B.
NOT, NOR, XOR
C.
NOT, OR, AND
D.
NOT, NOR XOR

Question 25

The amount of memory that is supported by any digital system depends upon.....

A.
The organization of memory
B.
The structure of memory
C.
The size of decoding unit
D.
The size of the address bus of the microprocessor

Question 26

Stack is an acronym for.....

A.
LIFO memory
B.
FIFO memory
C.
Flash memory
D.
Bust flash memory

Question 27

Addition of two octal numbers "36" and "71" results.....

A.
213
B.
123
C.
127
D.
345

Question 28

Addition of two octal numbers "567" and "243" results

A.
2013
B.
1023
C.
1027
D.
1032

Question 29

......is one of the examples of synchronous inputs.

A.
J-K input
B.
EN input
C.
Preset input (PRE)
D.
Clear Input (CLR)

Question 30

......occurs when the same clock signal arrives at different times at different clock input due to propagation delay.

A.
Race condition
B.
Clockskew
C.
Ripple effect
D.
None of the above

Question 31

In a state diagram, the transition from a current state to the next state is determined by.....

A.
Current state and the input
B.
Current state and output
C.
Previous state and inputs
D.
Previous state and output

Question 32

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

A.
1100
B.
0011
C.
0000
D.
1111

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