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Syllabus

NEC Computer · Practice

Chapters & sets

1. Basic Electrical and Electronics

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded System

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Concept of Computer Network and Network Security System

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

6. Theory of Computation and Computer Graphics

Theory of Computation

Set 150 Set 250 Set 360

Computer Graphics

Set 150 Set 251 Set 350 Set 450 Set 550

7. Data Structures and Algorithm, Database System and Operating System

8. Software Engineering and Object-Oriented Analysis & Design

Mixed chapter MCQs

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 750 Set 926

9. Artificial Intelligence and Neural Networks

Mixed chapter MCQs

Set 150 Set 317 Set 450 Set 550 Set 650 Set 750 Set 850 Set 932

10. Project Planning, Design and Implementation

Engineering Drawing

Set 150 Set 267

Engineering Economics

Set 168

Project Planning & Scheduling

Set 188

Project Mangement

Set 150

Engineering Professional Practice

Set 120

Engineering Regulatory Body

Set 130

Mixed chapter MCQs Set 10

50 questions

Question 1

Address symbol table is generated by

A.
Memory management software
B.
Assembler
C.
Match logic of associative memory
D.
Generated by operating system

Question 2

50

When an instruction is read from the memory, it is called

A.
Memory read cycle
B.
Fetch cycle
C.
Instruction cycle
D.
Memory write cycle

Question 3

Which activity does not take place during execution cycle?

A.
ALU performs the arithmetic and logical operation
B.
Effective address is calculated
C.
Next instruction is fetched
D.
Branch address is calculated and branching conditions are checked

Question 4

The time for which the D-input of a D-FF must not change after the clock is applied is known as

A.
Hold time
B.
Set-up time
C.
Transition time
D.
Delay time

Question 5

How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16?

A.
64
B.
16
C.
32
D.
128

Question 6

In addition of two signed numbers, represented in 2's complement form generates an overflow if

A.
A. B = 0
B.
A = 0
C.
A. B = 1
D.
A + B = 1

Question 7

In DMA the data transfer is controlled by...

A.
Microprocessor
B.
RAM
C.
Memory
D.
I/O devices

Question 8

Synchronous means...

A.
At irregular intervals
B.
At same time
C.
At variable time
D.
None of the above

Question 9

Excess-3 equivalent representation of (1234) H is

A.
(1237) Ex-3
B.
(4567) Ex-3
C.
(7993) Ex-3
D.
(4663) Ex-3

Question 10

Which of the memory holds the information when the Power Supply is switched off?

A.
Static RAM
B.
Dynamic RAM
C.
EEROM
D.
None of the above

Question 11

Minimum no. of NAND gate required implementing an Ex-OR function is

A.
2
B.
3
C.
4
D.
5

Question 12

Which of the following expression is not equivalent to x?

A.
x NAND x
B.
x NOR x
C.
x NAND 1
D.
x NOR 1

Question 13

BCD equivalent of Two's complement is

A.
Nine's complement
B.
One's complement+1
C.
Ten's complement
D.
None of the above

Question 14

Associative memory is sometimes called as...

A.
Virtual memory
B.
Cache memory
C.
Main memory
D.
Content addressable memory

Question 15

When CPU is not fully loaded, which of the following method of data transfer is preferred?

A.
DMA
B.
Interrupt
C.
Polling
D.
None of the above

Question 16

8085 microprocessor carryout the subtraction by

A.
BCD subtraction method
B.
Hexadecimal subtraction method
C.
2's complement method
D.
Floating Point subtraction method

Question 17

PAL circuit consists of

A.
Fixed OR & programmable AND logic
B.
Programmable OR & Fixed AND Logic
C.
Fixed OR & fixed AND logic
D.
Programmable OR & programmable AND logic

Question 18

CPU checks for an interrupt signal during

A.
Starting of last Machine cycle
B.
First T-State of interrupt cycle
C.
Last T-State of instruction cycle
D.
Fetch cycle

Question 19

Which of the following is not a characteristic of RISC architecture......?

A.
Larger instruction set
B.
Simple addressing mode
C.
One instruction per cycle
D.
Register to register operation

Question 20

Memory interleaving technique is used to address the memory modules in order to have

A.
Higher average utilization
B.
Faster access to a block of data
C.
Reduced complexity in mapping hardware
D.
Both (A) and (B)

Question 21

In a multiprogramming system, which of the following is used?

A.
Data parallelism
B.
L1 cache
C.
Paging concept
D.
None of the above

Question 22

Cycle stealing technique is used in

A.
Interrupt based data transfer
B.
DMA based data transfer
C.
Polled mode data transfer
D.
None of the above

Question 23

During DMA acknowledge cycle, CPU relinquishes

A.
Address bus only
B.
Control bus and data bus
C.
Address bus and control bus
D.
Data bus and address bus

Question 24

If the stack pointer is initialized with (4FEB) H, then after execution of Push operation in 8085 microprocessors, the Stack Pointer shall be

A.
4FEA
B.
4FEC
C.
4FED
D.
4FE9

Question 25

A more efficient way to organize a Page Table is by means of an associative memory having

A.
Number of words equal to number of pages
B.
Number of words more than the number of pages
C.
Number of words less than the number of pages
D.
Any one of the above

Question 26

If there are four ROM ICs of 8K and two RAM ICs of 4K words, then the address range of 1st RAM is (Assume initial addresses correspond to ROMs)

A.
(8000) H to (9FFF) H
B.
(8000) H to (8FFF) H
C.
(6000) H to (7FFF) H
D.
(9000) H to (9FFF) H

Question 27

A.B.C is equal to A B C for

A.
A=0, B=1, C=0
B.
A=1, B=0, C=1
C.
A=1, B=1, C=1
D.
All of the above

Question 28

Gray code equivalent of (1000)2 is

A.
1111
B.
1100
C.
1000
D.
None of the above

Question 29

The memory blocks are mapped on to the cache with the help of......

A.
Hash functions
B.
Vectors
C.
Mapping functions
D.
None of the above

Question 30

During a write operation if the required block is not present in the cache then...... occurs

A.
Write latency
B.
Write hit
C.
Write delay
D.
Write miss

Question 31

In...... protocol the information is directly written into main....

A.
Write through
B.
Write back
C.
Write first
D.
None of the above

Question 32

The method of mapping the consecutive memory blocks to consecutive cache blocks is called....

A.
Set associative
B.
Associative
C.
Direct
D.
Indirect

Question 33

While using the direct mapping technique, in a 16-bit system the higher order 5 bits is used for....

A.
Tag
B.
Block
C.
Word
D.
Id

Question 34

The technique of searching for a block by going through all tags is......

A.
Linear search
B.
Binary search
C.
Associative search
D.
None of the above

Question 35

In case of Zero-address instruction method the operands are stored in....

A.
Register
B.
Accumulators
C.
Push down stack
D.
Cache

Question 36

The addressing mode which makes use of in-direction pointer is......

A.
Indirect addressing mode
B.
Index addressing mode
C.
Relative addressing mode
D.
Offset addressing mode

Question 37

The addressing mode, where you directly specify the operand value is

A.
Immediate
B.
Direct
C.
Definite
D.
Relative

Question 38

...addressing mode is most suitable to change the normal sequence of execution of instructions.

A.
Relative
B.
Indirect
C.
Index with offset
D.
Immediate

Question 39

The pipelining process is also called as....

A.
Superscalar operation
B.
Assembly line operation
C.
Von Neumann cycle
D.
None of the mentioned

Question 40

The fetch and execution cycles are interleaved with the help of......

A.
Modification in processor architecture
B.
Clock
C.
Special unit
D.
Control unit

Question 41

The situation where in the data of operands are not available is called...

A.
Data hazard
B.
Stock
C.
Deadlock
D.
Structural hazard

Question 42

The reason for the implementation of the cache memory is

A.
To increase the internal memory of the system
B.
The difference in speeds of operation of the processor and memory
C.
To reduce the memory access and cycle time
D.
All of the above

Question 43

The effectiveness of the cache memory is based on the property of ______.

A.
Locality of reference
B.
Memory localization
C.
Memory size
D.
None of the above

Question 44

The temporal aspect of the locality of reference means

A.
That the recently executed instruction won't be executed soon
B.
That the recently executed instruction is temporarily not referenced
C.
That the recently executed instruction will be executed soon again
D.
None of the above

Question 45

The spatial aspect of the locality of reference means

A.
That the recently executed instruction is executed again next
B.
That the recently executed won't be executed again
C.
That the instruction executed will be executed at a later time
D.
That the instruction in close proximity of the instruction executed will be executed in future

Question 46

The algorithm to remove and place new contents into the cache is called ______.

A.
Renewal algorithm
B.
Updating
C.
Replacement algorithm
D.
None of the above

Question 47

The key factor/s in commercial success of a computer is/are......

A.
Performance
B.
Cost
C.
Speed
D.
Both A and B

Question 48

The main objective of the computer system is

A.
To provide optimal power operation
B.
To provide best performance at low cost
C.
To provide speedy operation at low power consumption
D.
All of the above

Question 49

A common measure of performance is:

A.
Price/performance ratio
B.
Performance /price ratio
C.
Operation/price ratio
D.
None of the above

Question 50

The main purpose of having memory hierarchy is to

A.
Reduce access time
B.
Provide large capacity
C.
Reduce propagation time
D.
Both A and B

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