Latest notices:

NEC licence exam preparation, made clearer.Practice questions, syllabus guides, and timed mocks for Nepal engineers.New study resources are added regularly.

Login Sign up

Syllabus

NEC Computer · Practice

Chapters & sets

1. Basic Electrical and Electronics

Basic Electrical

Set 1106

Basic Electronics

Set 171 Set 233

2. Digital Logic and Microprocessor

Digital Logic

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 749 Set 851 Set 950 Set 1050 Set 1150 Set 1232

Microprocessor

Set 150 Set 250 Set 350 Set 445 Set 550 Set 650 Set 720 Set 850 Set 969

3. Programming Language and Its Applications

Mixed chapter MCQs

Set 150 Set 249 Set 349 Set 451 Set 540

4. Computer Organization and Embedded System

Mixed chapter MCQs

Set 150 Set 249 Set 350 Set 450 Set 550 Set 650 Set 750 Set 849 Set 950 Set 1050 Set 1150

5. Concept of Computer Network and Network Security System

Basic Networking

Set 150 Set 253

Advanced Networking

Set 150 Set 250 Set 350 Set 450 Set 550 Set 655

6. Theory of Computation and Computer Graphics

Theory of Computation

Set 150 Set 250 Set 360

Computer Graphics

Set 150 Set 251 Set 350 Set 450 Set 550

7. Data Structures and Algorithm, Database System and Operating System

8. Software Engineering and Object-Oriented Analysis & Design

Mixed chapter MCQs

Set 150 Set 250 Set 350 Set 450 Set 550 Set 650 Set 750 Set 926

9. Artificial Intelligence and Neural Networks

Mixed chapter MCQs

Set 150 Set 317 Set 450 Set 550 Set 650 Set 750 Set 850 Set 932

10. Project Planning, Design and Implementation

Engineering Drawing

Set 150 Set 267

Engineering Economics

Set 168

Project Planning & Scheduling

Set 188

Project Mangement

Set 150

Engineering Professional Practice

Set 120

Engineering Regulatory Body

Set 130

Digital Logic Set 8

51 questions

Question 1

An exclusive-OR function is expressed as:

A.
$AB + \overline{A}B$
B.

50

(A + B)(\overline{A} + \overline{B})

C.

\overline{A}B + A\overline{B}

D.

(A + B) + (\overline{A} + \overline{B})

Question 2

The AND operation can be produced with:

A.
$\text{Two AND gates}$
B.
$\text{One NOR gate}$
C.
$\text{Three NAND gates}$
D.
$\text{Three NOR gates}$

Question 3

The OR operation can be produced with:

A.
$\text{Two NOR gates}$
B.
$\text{Four NAND gates}$
C.
$\text{Three NAND gates}$
D.
$\text{Both answers A and B}$

Question 4

When using dual symbols in a logic diagram:

A.
$\text{Bubble outputs are connected to bubble inputs}$
B.
$\text{The NAND symbol produces the NAND operation}$
C.
$\text{The negative-OR symbol produces the OR operation}$
D.
$\text{All of these answers are true}$

Question 5

All Boolean expressions can be implemented with:

A.
$\text{NAND gates only}$
B.
$\text{NOR gates only}$
C.
$\text{Combinations of NAND and NOR gates}$
D.
$\text{Any of these}$

Question 6

The device used to convert a binary number to a 7-segment display format is:

A.
$\text{Multiplexer}$
B.
$\text{Decoder}$
C.
$\text{Encoder}$
D.
$\text{Register}$

Question 7

An example of a data storage device is:

A.
$\text{Two inputs and two outputs}$
B.
$\text{Two inputs and three outputs}$
C.
$\text{Three inputs and two outputs}$
D.
$\text{Two inputs and one output}$

Question 8

A full-adder is characterized by:

A.
$\text{Two inputs and two outputs}$
B.
$\text{Two inputs and three outputs}$
C.
$\text{Three inputs and two outputs}$
D.
$\text{Two inputs and one output}$

Question 9

The inputs to a full-adder are

A = 1

,

B = 1

, and

C_{in} = 0

. The outputs are:

A.
$S = 1, C_{out} = 1$
B.
$S = 0, C_{out} = 1$

Question 10

A 4-bit parallel adder can add:

A.
$\text{Two 4-bit binary numbers}$
B.
$\text{Four bits at a time}$
C.
$\text{Two 2-bit binary numbers}$
D.
$\text{Four bits in sequence}$

Question 11

The 74LS83A is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder, you must:

A.
$\text{Use four adders with no interconnections}$
B.
$\text{Use two adders and connect the sum outputs of one to the bit inputs of the other}$
C.
$\text{Use eight adders with no interconnections}$
D.
$\text{Use two adders with the carry output of one connected to the carry input of the other}$

Question 12

If a 74HC85 magnitude comparator has

A = 1011

and

B = 1001

on its inputs, the outputs are:

A.
$A > B = 0, A < B = 1, A = B = 0$
B.
$A > B = 1, A < B = 0, A = B = 0$
C.
$A > B = 1, A < B = 0, A = B = 0$
D.
$A > B = 0, A < B = 0, A = B = 1$

Question 13

If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what are the inputs?

A.
$A_3A_2A_1A_0 = 1010$
B.
$A_3A_2A_1A_0 = 1100$
C.
$A_3A_2A_1A_0 = 1110$
D.
$A_3A_2A_1A_0 = 0100$

Question 14

A BCD-to-7 segment decoder has

0100

on its inputs. The active outputs are:

A.
$a, c, f, g$
B.
$b, c, e, f$
C.
$b, c, f, g$
D.
$b, d, e, g$

Question 15

If an octal-to-binary priority encoder has its 0, 2, 5, and 6 inputs at the active level, the active-HIGH binary output is:

A.
$110$
B.
$10$
C.
$010$
D.
$000$

Question 16

In general, a multiplexer has:

A.
$\text{One data input, several data outputs, and selection inputs}$
B.
$\text{One data input, one data output, and one selection input}$
C.
$\text{Several data inputs, several data outputs, and selection inputs}$
D.
$\text{Several data inputs, one data output, and selection inputs}$

Question 17

Data selectors are basically the same as:

A.
$\text{Decoders}$
B.
$\text{Multiplexers}$
C.
$\text{De-multiplexers}$
D.
$\text{Encoders}$

Question 18

Which of the following codes exhibit even parity?

A.
$10011000$
B.
$11111$
C.
$01111000$
D.
$\text{Both answer (A) and (B)}$

Question 19

If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be:

A.
$\text{Set}$
B.
$\text{Invalid}$
C.
$\text{Reset}$
D.
$\text{Clear}$

Question 20

The invalid state of an S-R latch occurs when:

A.
$S = 1, R = 0$
B.
$S = 1, R = 1$
C.
$S = 0, R = 1$
D.
$S = 0, R = 0$

Question 21

For a gated D latch, the Q output always equals the D input:

A.
$\text{Before the enable pulse}$
B.
$\text{Immediately after the enable pulse}$
C.
$\text{During the enable pulse}$
D.
$\text{Answers (B) and (C)}$

Question 22

Like the latch, the flip-flop belongs to a category of logic circuits known as:

A.
$\text{Monostable multivibrators}$
B.
$\text{Astable multivibrators}$
C.
$\text{Bistable multivibrators}$
D.
$\text{One-shot}$

Question 23

The purpose of the clock input to a flip-flop is to:

A.
$\text{Clear the device}$
B.
$\text{Set the device}$
C.
$\text{Always cause the output to change state}$
D.
$\text{Cause the output to assume a state dependent on the controlling (S-R, J-K, or D) inputs}$

Question 24

For an edge-triggered D flip-flop:

A.
$\text{A change in the state of the flip-flop can occur only at a clock pulse edge}$
B.
$\text{The state that the flip-flop goes to depends on the D input}$
C.
$\text{The output follows the input at each clock pulse}$
D.
$\text{All of these answers}$

Question 25

A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the:

A.
$\text{Toggle condition}$
B.
$\text{Type of clock}$
C.
$\text{Preset input}$
D.
$\text{Clear input}$

Question 26

A flip-flop is in the toggle condition when:

A.
$J = 1, K = 0$
B.
$J = 0, K = 0$
C.
$J = 1, K = 1$
D.
$J = 0, K = 1$

Question 27

A J-K flip-flop with

J = 1

and

K = 1

has a 10 kHz clock input. The Q output is:

A.
$\text{Constantly HIGH}$
B.
$\text{A 10 kHz square wave}$
C.
$\text{Constantly LOW}$
D.
$\text{A 5 kHz square wave}$

Question 28

Asynchronous counters are known as:

A.
$\text{Ripple counters}$
B.
$\text{Decade counters}$
C.
$\text{Multiple clock counters}$
D.
$\text{Modulus counters}$

Question 29

An asynchronous counter differs from a synchronous counter in:

A.
$\text{The number of states in its sequence}$
B.
$\text{The type of flip-flop used}$
C.
$\text{The method of clocking}$
D.
$\text{The value of the modulus}$

Question 30

The modulus of a counter is:

A.
$\text{The number of flip-flops}$
B.
$\text{The actual number of times it recycles in a second}$
C.
$\text{The number of times it recycles in a second}$
D.
$\text{The maximum possible number of states}$

Question 31

A 3-bit binary counter has a maximum modulus of:

A.
$3$
B.
$8$
C.
$6$
D.
$16$

Question 32

A 4-bit binary counter has a maximum modulus of:

A.
$16$
B.
$8$
C.
$32$
D.
$4$

Question 33

A modulus-12 counter must have:

A.
$12 \text{ flip-flops}$
B.
$4 \text{ flip-flops}$
C.
$3 \text{ flip-flops}$
D.
$\text{Synchronous clocking}$

Question 34

Which one of the following is an example of a counter with a truncated modulus?

A.
$\text{Modulus 8}$
B.
$\text{Modulus 16}$
C.
$\text{Modulus 14}$
D.
$\text{Modulus 32}$

Question 35

A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total of:

A.
$12 \text{ ns}$
B.
$48 \text{ ns}$
C.
$24 \text{ ns}$
D.
$36 \text{ ns}$

Question 36

A BCD counter is an example of:

A.
$\text{A full-modulus counter}$
B.
$\text{A truncated-modulus counter}$
C.
$\text{A decade counter}$
D.
$\text{Answers (A) and (C)}$

Question 37

Which of the following is an invalid state in an 8421 BCD counter?

A.
$1100$
B.
$0101$
C.
$0010$
D.
$1000$

Question 38

Three cascaded modulus-10 counters have an overall modulus of:

A.
$30$
B.
$1000$
C.
$100$
D.
$10,000$

Question 39

A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5 counter, a modulus-8 counter, and two modulus-10 counters. The lowest output frequency possible is:

A.
$10 \text{ kHz}$
B.
$5 \text{ kHz}$
C.
$2.5 \text{ kHz}$
D.
$25 \text{ kHz}$

Question 40

A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is:

A.
$0001$
B.
$1000$
C.
$1111$
D.
$1110$

Question 41

The terminal count of a modulus-13 binary counter is:

A.
$0000$
B.
$1101$
C.
$1111$
D.
$1100$

Question 42

A stage in a shift register consists of:

A.
$\text{A latch}$
B.
$\text{A byte of storage}$
C.
$\text{A flip-flop}$
D.
$\text{Four bits of storage}$

Question 43

To serially shift a byte of data into a shift register, there must be:

A.
$\text{One clock pulse}$
B.
$\text{Eight clock pulses}$
C.
$\text{One load pulse}$
D.
$\text{One clock pulse for each 1 in the data}$

Question 44

To parallel load a byte of data into a shift register with a synchronous load, there must be:

A.
$\text{One clock pulse}$
B.
$\text{Eight clock pulses}$
C.
$\text{One clock pulse for each 1 in the data}$
D.
$\text{One clock pulse for each 1 in the data}$

Question 45

The group of bits 101101101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains:

A.
$01011110$
B.
$11110010$
C.
$10110101$
D.
$00101101$

Question 46

With a 1 MHz clock frequency, eight bits can be serially entered into a shift register in:

A.
$80 \text{ µs}$
B.
$80 \text{ ms}$
C.
$8 \text{ µs}$
D.
$10 \text{ µs}$

Question 47

With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register:

A.
$\text{In 80 µs}$
B.
$\text{In the propagation delay time of eight flip-flops}$
C.
$\text{In 1 µs}$
D.
$\text{In the propagation delay time of one flip-flop}$

Question 48

A modulus-10 Johnson counter requires:

A.
$\text{Ten flip-flops}$
B.
$\text{Five flip-flops}$
C.
$\text{Four flip-flops}$
D.
$\text{Twelve flip-flops}$

Question 49

A modulus-10 ring counter requires a minimum of:

A.
$\text{Ten flip-flops}$
B.
$\text{Four flip-flops}$
C.
$\text{Five flip-flops}$
D.
$\text{Twelve flip-flops}$

Question 50

When an 8-bit serial in/serial out shift register is used for a 24 µs time delay, the clock frequency must be:

A.
$41.67 \text{ kHz}$
B.
$125 \text{ kHz}$
C.
$333 \text{ kHz}$
D.
$8 \text{ MHz}$

Question 51

The bit capacity of a memory that has 1024 addresses and can store 8 bits at each address is:

A.
$1024$
B.
$8$
C.
$8192$
D.
$4096$

Practice another set Take a test on this chapter →

C.

S = 1, C_{out} = 0

D.

S = 0, C_{out} = 0